A semiconductor memory device has a structure in which a memory cell array that includes multiple memory cells and a peripheral circuit that drives the memory cell array are integrated. For example, the memory cell of the semiconductor memory device includes a charge storage layer disposed between a semiconductor channel and a word line. In the case where the interconnects of these are formed using a metal or the like for the memory cells, the front surface of the wafer warps greatly due to stress such as compressive stress, tensile stress, etc., generated in the interconnects. In the case where the interconnects are arranged in multiple directions in the front surface of the wafer, it is difficult to reduce the warp of the wafer because the directions of the stress generated in the interconnects are different.